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general description the max5037a dual-phase, pwm controller provides high-output-current capability in a compact package with a minimum number of external components. the max5037a utilizes a dual-phase, average-current-mode control that enables optimal use of low r ds(on) mosfets, eliminating the need for external heatsinks even when delivering high output currents. differential sensing enables accurate control of the output voltage, while adaptive voltage positioning provides optimum transient response. an internal regula- tor enables operation with either +5v or +12v input volt- age without the need for additional voltage sources. the high switching frequency, up to 500khz per phase, and dual-phase operation allow the use of low output induc- tor values and input capacitor values. this accommo- dates the use of pc board-embedded planar magnetics achieving superior reliability, current sharing, thermal management, compact size, and low system cost. the max5037a also features a clock input (clkin) for synchronization to an external clock, and a clock output (clkout) with programmable phase delay (relative to clkin) for paralleling multiple phases. the max5037a also limits the reverse current in case the bus voltage becomes higher than the regulated output voltage. the max5037a operates over the extended temperature range (-40? to +85?) and is available in 44-pin mqfp or thin qfn packages. refer to the max5038a/ max5041a and max5065/max5067 data sheets for either a fixed output voltage controller or an adjustable output voltage controller in an ssop or thin qfn package. applications servers and workstations point-of-load high-current/high-density telecom dc-dc regulators networking systems large-memory arrays raid systems high-end desktop computers features ? +4.75v to +5.5v or +8v to +28v input voltage range ? up to 60a output current ? internal voltage regulator for a +12v or +24v power bus ? internal 5-bit dac vid control (vrm 9.0/vrm 9.1 compliant, 0.8% accuracy) ? programmable adaptive output voltage positioning ? true differential remote output sensing ? out-of-phase controllers reduce input capacitance requirement and distribute power dissipation ? average-current-mode control superior current sharing between individual phases and paralleled modules accurate current limit eliminates mosfet and inductor derating ? limits reverse-current sinking in paralleled modules ? integrated high-output-current gate drivers ? selectable fixed frequency 250khz or 500khz per phase (up to 1mhz for two phases) ? external frequency synchronization from 125khz to 600khz ? internal pll with clock output for paralleling multiple dc-dc converters ? power-good output ? phase failure detector (patent pending) ? overvoltage and thermal protection ? 44-pin mqfp or thin qfn packages max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ________________________________________________________________ maxim integrated products 1 19-3033; rev 1; 4/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin-package MAX5037AEMH -40? to +85? 44 mqfp max5037aeth -40? to +85? 44 thin qfn pin configuration appears at end of data sheet.
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = v dd = +5v, circuit of figure 1, t a = -40? to +85?, unless otherwise noted. typical specifications are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to sgnd.............................................................-0.3v to +30v bst_ to sgnd. .-0.3v to +35v dh_ to lx_ .................................-0.3v to [(v bst _ - v lx _) + 0.3v] dl_ to pgnd ..............................................-0.3v to (v dd + 0.3v) bst_ to lx_ ..............................................................-0.3v to +6v v cc to sgnd............................................................-0.3v to +6v v dd to pgnd............................................................-0.3v to +6v sgnd to pgnd .....................................................-0.3v to +0.3v all other pins to sgnd...............................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70?) 44-pin mqfp (derate 12.7mw/? above +70?).......1013mw 44-pin thin qfn (derate 27.0mw/? above +70?) ........................................................... 2162.2mw package thermal resistance, jc (thin qfn only) ........+2?/w operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units system specifications 828 input voltage range v in short in and v cc together for 5v input operation 4.75 5.5 v quiescent supply current i q en = v cc or sgnd, vid inputs unconnected 46ma efficiency i load = 52a (26a per phase) 90 % startup/internal regulator v cc undervoltage lockout uvlo v cc rising 4.0 4.15 4.5 v v cc undervoltage lockout hysteresis 200 mv v cc output accuracy v in = 8v to 28v, i source = 0 to 80ma 4.85 5.1 5.30 v v out /adaptive voltage positioning (avp) r reg = r f = 100k ? , r in = 1k ? , no load, figure 3 -0.8 +0.8 nominal output voltage accuracy (vid setting) v in = v cc = 4.75v to 5.5v, or v in = 8v to 28v, r reg = r f = 100k ? , r in = 1k ? , no load, figure 3 -1 +1 % maximum reg loading i reg_max 50 ? t a = 0? to +85? -3 +3 reg accuracy (voltage positioning) d ( ? v out ) t a = -40? to +85? -5 +5 % maximum cntr loading i cntr_max 50 ? t a = 0? to +85? -3 +3 center voltage set-point accuracy (note 2) d ( ? v cntr ) t a = -40? to +85? -5 +5 % mosfet drivers output driver impedance r on low or high output 1 3 ? output driver peak source/sink current i dh _, i dl _ 4a
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = v dd = +5v, circuit of figure 1, t a = -40? to +85?, unless otherwise noted. typical specifications are at t a = +25?.) (note 1) parameter symbol conditions min typ max units nonoverlap time t no c dh _ /dl _ = 5nf 60 ns oscillator and pll clkin = sgnd 238 250 262 switching frequency f sw clkin = v cc 475 500 525 khz pll lock range f pll 125 600 khz pll locking time t pll 200 ? phase = v cc 115 120 125 phase = unconnected 85 90 95 clkout phase shift (at f sw = 125khz) = + = ( ) = ( ) current limit average current-limit threshold v cl csp_ to csn_ 45 48 51 mv reverse current-limit threshold v clr csp_ to csn_ -3.9 -0.2 mv cycle-by-cycle current limit v clpk csp_ to csn_ (note 3) 90 112 130 mv cycle-by-cycle overload response time t r v csp _ to v csn _ = +150mv 260 ns current-sense amplifier csp_ to csn_ input resistance r cs _4k ? common-mode range v cmr ( cs ) -0.3 +3.6 v input offset voltage v os ( cs ) -1 +1 mv amplifier gain a v(cs) 18 v/v 3db bandwidth f 3db 4mhz current-error amplifier (transconductance amplifier) transconductance gm ca 550 ? open-loop gain a vol ( ce ) no load 50 db differential voltage amplifier (diff) common-mode voltage range v cmr ( diff ) -0.3 +1.0 v diff output voltage v cm v sense+ = v sense- = 0 0.6 v input offset voltage v os ( diff ) -2 +2 mv amplifier gain a v ( diff ) 0.997 1 1.003 v/v 3db bandwidth f 3db c diff = 20pf 3 mhz minimum output current drive i out ( diff ) 1.0 ma
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = v dd = +5v, circuit of figure 1, t a = -40? to +85?, unless otherwise noted. typical specifications are at t a = +25?.) (note 1) parameter symbol conditions min typ max units sense+ to sense- input resistance r vs _50 100 k ? voltage-error amplifier (eaout) open-loop gain a vol ( ea ) 70 db unity-gain bandwidth f ugea 3 mhz ean input bias current i b(ea) cntr and reg = open, v ean = 2.0v -100 +100 na error-amplifier output clamping voltage v clamp ( ea ) with respect to v cm 810 918 mv power-good, phase failure detection, overvoltage protection, and thermal shutdown v ov +6 +8 +10 pgood trip level v uv pgood goes low when v out is outside of this window -12.5 -10 -8.5 % v o (vid) pgood output low level v pglo i sink = 4ma 0.20 v pgood output leakage current i pg pgood = v cc 1a phase failure trip threshold v ph pgood goes low when clp_ is higher than v ph 2.0 v ovpin trip threshold ovp th above vid programmed output voltage +10 +13 +16 % v o (vid) ovpout source/sink current i ovpout v ovpout = 2.5v 15 20 ma ovpin input resistance r ovpin 190 280 370 k ? thermal shutdown t shdn 150 ? thermal-shutdown hysteresis 8c logic inputs for vid logic-input pullup resistors r vid 81220k ? logic-input low voltage v il 0.8 v logic-input high voltage v ih 1.7 v vid internal pullup voltage v vid all vid_ inputs unconnected 2.8 2.9 3.2 v en input en input low voltage v enl 1v en input high voltage v enh 3v en pullup current i en 4.5 5 5.5 ? note 1: specifications from -40? to 0? are guaranteed by characterization but not production tested. note 2: cntr voltage accuracy is defined as the center of the adaptive voltage-positioning window (see adaptive voltage positioning section). note 3: guaranteed by design. not production tested. note 4: see peak-current comparator section.
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller _______________________________________________________________________________________ 5 efficiency vs. output current and internal oscillator frequency max5037a toc01 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 60 70 80 90 100 40 052 f = 500khz f = 250khz v in = +5v v out = +1.8v efficiency vs. output current and input voltage max5037a toc02 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v in = +12v v in = +5v v out = +1.8v f sw = 250khz efficiency vs. output current max5037a toc03 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v in = +24v v out = +1.8v f sw = 125khz efficiency vs. output current and output voltage max5037a toc04 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v out = +1.1v v out = +1.5v v out = +1.8v v in = +12v f sw = 250khz efficiency vs. output current and output voltage max5037a toc05 i out (a) (%) 48 44 40 36 32 28 24 20 16 12 8 4 50 40 30 20 10 60 70 80 90 100 0 052 v out = +1.1v v out = +1.5v v out = +1.8v v in = +5v f sw = 500khz supply current vs. frequency and input voltage max5037a toc06 frequency (khz) i cc (ma) 550 500 400 450 200 250 300 350 150 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 6.0 100 600 v in = +24v v in = +12v v in = +5v externalclock no driver load supply current vs. temperature and frequency max5037a toc07 temperature ( c) i cc (ma) 60 35 10 -15 10 20 30 40 50 60 70 80 90 100 0 -40 85 250khz 125khz v in = +12v c dl_ = 22nf c dh_ = 8.2nf supply current vs. temperature and frequency max5037a toc08 temperature ( c) i cc (ma) 60 35 10 -15 50 75 100 125 150 175 25 -40 85 600khz 500khz v in = +5v c dl_ = 22nf c dh_ = 8.2nf supply current vs. load capacitance per driver max5037a toc09 c driver (nf) i cc (ma) 13 11 7 9 5 3 10 20 30 40 50 60 70 80 90 100 0 115 v in = +12v f sw = 250khz t ypical operating characteristics (circuit of figure 1, t a = +25?, unless otherwise noted.)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.) current-sense threshold vs. output voltage max5037a toc10 v out (v) (v csp_ - v csn_ ) (mv) 1.7 1.6 1.4 1.5 1.2 1.3 1.1 46 47 48 49 50 51 52 53 54 55 45 1.0 1.8 phase 2 phase 1 overvoltage threshold (pgood) vs. input voltage max5037a toc11 v in (v) v ov (v) 5.20 5.15 5.05 5.10 4.85 4.90 4.95 5.00 4.80 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 1.0 4.75 5.25 v out = +1.8v v out = +1.1v overvoltage threshold (ovpout) vs. input voltage max5037a toc12 v in (v) ovp th (v) 5.20 5.15 5.05 5.10 4.85 4.90 4.95 5.00 4.80 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 4.75 5.25 v out = +1.8v v out = +1.1v undervoltage threshold (pgood) vs. input voltage max5037a toc13 v in (v) v uv (v) 5.20 5.15 5.05 5.10 4.85 4.90 4.95 5.00 4.80 0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65 1.75 4.75 5.25 v out = +1.8v v out = +1.1v output voltage vs. i load and r cntr max5037a toc14 i load (a) v out (v) 50 45 40 35 30 25 20 15 10 5 1.65 1.70 1.75 1.80 1.85 1.90 1.60 055 r cntr = 50k ? r cntr = 100k ? r cntr = r cntr = 200k ? v in = +12v vid setting = +1.75v output voltage vs. i load and r cntr max5037a toc15 i load (a) v out (v) 50 45 40 35 30 25 20 15 10 5 1.35 1.30 1.25 1.40 1.45 1.50 1.55 1.60 1.20 055 r cntr = 50k ? r cntr = 100k ? r cntr = r cntr = 200k ? v in = +12v vid setting = +1.4v output voltage vs. output current and error amp gain (r f / r in ) max5037a toc16 i load (a) v out (v) 50 45 40 35 30 25 20 15 10 5 1.65 1.70 1.75 1.80 1.85 1.60 055 v in = +12v v out = +1.8v r f / r in = 15 r f / r in = 12.5 r f / r in = 10 r f / r in = 7.5 differential amplifier bandwidth max5037a toc17 frequency (mhz) gain (v/v) phase (degrees) 1 0.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.01 10 -225 -270 -180 -135 -90 -45 0 45 90 phase gain diff output error vs. sense+ to sense- voltage max5037a toc18 ? v sense (v) error (%) 1.9 1.8 1.1 1.2 1.3 1.5 1.6 1.4 1.7 0.025 0.050 0.075 0.100 0.125 0.150 0.175 0.200 0 1.0 2.0 v in = +12v no driver
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller _______________________________________________________________________________________ 7 v cc load regulation vs. input voltage max5037a toc19 i cc (ma) v cc (v) 135 120 15 30 45 75 90 60 105 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 4.80 0 150 v in = +24v v in = +12v v in = +8v dc load v cc line regulation max5037a toc20 v in (v) v cc (v) 26 24 20 22 12 14 16 18 10 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 4.75 828 i cc = 0 i cc = 40ma v cc line regulation max5037a toc21 v in (v) v cc (v) 13 12 91011 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 4.75 8 i cc = 80ma driver rise time vs. driver load capacitance max5037a toc22 c driver (nf) t r (ns) 31 26 16 21 11 6 10 20 30 40 50 60 70 80 90 100 110 120 0 136 dl_ dh_ v in = +12v f sw = 250khz driver fall time vs. driver load capacitance max5037a toc23 c driver (nf) t r (ns) 31 26 16 21 11 6 10 20 30 40 50 60 70 80 90 100 110 120 0 136 dl_ dh_ v in = +12v f sw = 250khz 100ns/div high-side driver (dh_) sink and source current dh_ 1.6a/div max5037a toc24 v in = +12v c dh_ = 22nf 100ns/div low-side driver (dl_) sink and source current dl_ 1.6a/div max5037a toc25 v in = +12v c dl_ = 22nf 100 s/div pll locking time 250khz to 350khz and 350khz to 250khz clkout 5v/div max5037a toc26 pllcmp 200mv/div v in = +12v no load 350khz 250khz 0 100 s/div pll locking time 250khz to 500khz and 500khz to 250khz clkout 5v/div max5037a toc27 pllcmp 200mv/div 0 v in = +12v no load 500khz 250khz t ypical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.) 100 s/div pll locking time 250khz to 150khz and 150khz to 250khz clkout 5v/div max5037a toc28 pllcmp 200mv/div 0 v in = +12v no load 250khz 150khz 40ns/div high-side driver (dh_) rise time max5037a toc29 v in = +12v c dh_ = 22nf dh_ 2v/div 40ns/div high-side driver (dh_) fall time max5037a toc30 dh_ 2v/div v in = +12v c dh_ = 22nf 40ns/div low-side driver (dl_) rise time max5037a toc31 dl_ 2v/div v in = +12v c dl_ = 22nf 40ns/div low-side driver (dl_) fall time max5037a toc32 dl_ 2v/div v in = +12v c dl_ = 22nf 500ns/div output ripple max5037a toc33 v out (ac-coupled) 10mv/div v in = +12v v out = +1.75v i out = 52a 2ms/div input startup response max5037a toc34 v in 5v/div v in = +12v v out = +1.75v i out = 52a v pgood 1v/div v out 1v/div 1ms/div enable startup response max5037a toc35 v en 2v/div v pgood 1v/div v out 1v/div v in = +12v v out = +1.75v i out = 52a 40 s/div load-transient response max5037a toc36 v in = +12v v out = +1.75v i step = 8a to 52a t rise = 1 s v out 50mv/div
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller _______________________________________________________________________________________ 9 t ypical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.) reverse-current sink vs. temperature max5037a toc37 temperature ( c) i reverse (a) 60 35 10 -15 2.4 2.5 2.6 2.7 2.8 2.3 -40 85 v external = +3.3v v external = +2v v in = +12v v out = +1.5v r1 = r2 = 1.5m ? 200 s/div reverse-current sink at input turn-on max5037a toc38 v in = +12v v out = +1.5v v external = 2.5v reverse current 5a/div 0a r1 = r2 = 1.5m ? 200 s/div reverse-current sink at input turn-on max5037a toc39 v in = +12v v out = +1.5v v external = 3.3v reverse current 10a/div 0a r1 = r2 = 1.5m ? 200 s/div reverse-current sink at enable turn-on max5037a toc40 v in = +12v v out = +1.5v v external = 2.5v reverse current 5a/div 0a r1 = r2 = 1.5m ? 200 s/div reverse-current sink at enable turn-on max5037a toc41 v in = +12v v out = +1.5v v external = 3.3v reverse current 10a/div 0a r1 = r2 = 1.5m ?
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 10 ______________________________________________________________________________________ pin description pin name function 1?, 44 vid3?id0, vid4 dac code inputs. vid0 is the lsb and vid4 is the msb for the internal 5-bit dac (table 1). connect to sgnd for logic low or leave open circuit for logic high. these inputs have 12k ? internal pullup resistors to an internal 3v regulator. 5, 20, 35 sgnd signal ground. ground connection for the internal circuitry. qfn package exposed pad connected to sgnd. 6 ovpin overvoltage protection circuit input. connect diff to ovpin. when ovpin exceeds +13% above the vid programmed output voltage, ovpout latches dh_ low and dl_ high. toggle en low to high or recycle the power to reset the latch. 7, 43 clp1, clp2 current-error amplifier output. compensate the current loop by connecting an r-c network to ground. 8 ovpout overvoltage protection output. use the ovpout active-high, push-pull output to trigger a safety device such as an scr. 9p good power-good output. the open-drain, active-low pgood output goes low when the vid programmed output voltage falls out of regulation or a phase failure is detected. the power-good window comparator thresholds are +8% and -10% of the vid programmed output voltage. forcing en low also forces pgood low. 10 sense+ differential output voltage-sensing positive input. used to sense a remote load. connect sense+ to v out+ at the load. the device regulates the difference between sense+ and sense- according to the programmed vid code and adaptive voltage positioning. 11 sense- differential output voltage-sensing negative input. used to sense a remote load. connect sense- to v out- or pgnd at the load. 12 diff differential remote-sense amplifier output. diff is the output of a precision unity-gain amplifier. 13 ean voltage-error amplifier inverting input. receives the output of the differential remote-sense amplifier. referenced to sgnd. 14 eaout voltage-error amplifier output. connect to an external, gain-setting feedback resistor. the error amplifier gain determines the output voltage load regulation for adaptive voltage positioning. 15 reg reg input. a resistor on reg applies the same voltage-positioning window at different vrm voltage settings. for a no-load output voltage (v core ) equal to vid, set r reg = r f , where the r f is the feedback resistor of the voltage-error amplifier. v reg internally regulates to the programmed vid output voltage. 16, 39 csp1, csp2 current-sense differential amplifier positive input. senses the inductor current. the differential voltage between csp_ and csn_ is amplified internally by the current-sense amplifier gain of 18. 17, 40 csn1, csn2 current-sense differential amplifier negative input. together with csp_, senses the inductor current. 18 cntr adaptive voltage center position input. connect a resistor between cntr and sgnd to program the center of the adaptive v out position. v cntr regulates to +1.22v. 19 en output enable. a logic low shuts down the power drivers. en has an internal 5? pullup current. 21, 33, 37 n.c. no connection. not internally connected. 22, 34 bst1, bst2 boost flying-capacitor connection. reservoir capacitor connection for the high-side fet driver supply. connect a 0.47? ceramic capacitor between bst_ and lx_. 23, 32 dh1, dh2 high-side gate-driver output. drives the gate of the high-side mosfet.
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 11 pin description (continued) pin name function 24, 31 lx1, lx2 inductor connection. source connection for the high-side mosfets. also serves as the return terminal for the high-side driver. 25, 30 dl1, dl2 low-side gate-driver output. synchronous mosfet gate drivers for the two phases. 26 v dd supply voltage for low-side and high-side drivers. v cc powers v dd . connect a parallel combination of 0.1? and 1? ceramic capacitors to pgnd and a 1 ? resistor to v cc to filter out the high peak currents of the driver from the internal circuitry. 27 v cc internal 5v regulator output. v cc is derived internally from the in voltage. bypass to sgnd with 4.7? and 0.1? ceramic capacitors. 28 in supply voltage connection. connect in to v cc for a 5v system. 29 pgnd power ground. connect pgnd, low-side synchronous mosfet? source, and v dd bypass capacitor returns together. 36 clkout oscillator output. clkout is phase shifted from clkin by the amount specified by phase. use clkout to parallel additional max5037s. 38 clkin cmos logic clock input. drive the internal oscillator with a frequency range between 125khz and 600khz. connect to v cc or sgnd. connect clkin to sgnd to set the internal oscillator to 250khz or connect to v cc to set the internal oscillator to 500khz. clkin has an internal 5? pulldown current. 41 phase phase shift setting input. drive phase high for 120? leave phase unconnected for 90? and force phase low for 60?of phase shift between the rising edges of clkout and clkin/dh1. 42 pllcmp external loop-compensation input. connect compensation network for the phase-locked loop (see phase-locked loop section).
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 12 ______________________________________________________________________________________ max5037a in en phase 1 csp1 drv_v cc ramp1 gm in clk clp1 csn1 ovpout shdn bst1 pgood dl1 lx1 dh1 v cc to internal circuits v dd csp1 csn1 clp1 phase 2 csp2 drv_v cc gm in clk clp2 csn2 shdn bst2 dl2 lx2 dh2 csp2 csn2 clp2 phase- locked loop ramp generator ramp2 clkin phase clkout pllcmp power- good generator diff clp1 clp2 dac_out n ovp comp 13% of dac_out diff amp error amp sense- sense+ diff adaptive voltage positioning rom voltage- positioning dac vid0 vid1 vid2 vid3 vid4 ean reg cntr ovpin eaout dac_out pgnd pgnd pgnd sgnd +0.6v +5v ldo regulator uvlo por temp sensor functional diagram
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 13 detailed description the max5037a (figures 1 and 2) average-current- mode pwm controller drives two out-of-phase buck converter channels. average-current-mode control improves current sharing between the channels while minimizing component derating and size. parallel multi- ple max5037a regulators to increase the output current capacity. for maximum ripple rejection at the input, set t he phase shift between phases to 90 for two paralleled converters, or 60 for three paralleled converters. the paralleling capability of the max5037a improves design flexibility in applications requiring upgrades (higher load). the programmable output voltage utilizes vid codes compliant with intel? vrm 9.0/vrm 9.1 specifications. max5037a q4 q3 c39 c40 r3 d2 q2 d1 v in c8?11 q1 v in v in = +5v v cc d4 d3 c41 c12 c38 c3?7 5 x 22 f c14, c15 c16?25 c26?30, c37 load v out = +1.1v to +1.85v at 52a l2 r2 l1 r1 23 dh1 24 lx1 25 dl1 22 bst1 27 v cc 28 v dd 32 dh2 31 lx2 30 dl2 34 bst2 csp2 csn2 pgood phase sgnd pgnd clp2 clp1 r11 pgood v cc r6 c35 c36 r5 c33 c34 39 40 9 41 5, 20, 35 29 43 7 c42 c1, c2 r13 v cc c31 c32 r4 csp1 16 csn1 17 sense+ 10 sense- 11 in 28 clkin 38 pllcmp 42 en 19 r10 r8 r7 r9 r12 c43 v in dac inputs 18 cntr 15 reg 14 eaout 13 ean 12 diff 6 ovpin 8 ovpout 4 vid0 3 vid1 2 vid2 1 vid3 44 vid4 *see table 2 for component values. c13 in in figure 1. typical vrm application circuit, v in = +5v
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 14 ______________________________________________________________________________________ dual-phase converters with an out-of-phase locking arrangement reduce the input and output capacitor rip- ple current, effectively multiplying the switching fre- quency by the number of phases. each phase of the max5037a consists of an inner average current loop controlled by a common outer-loop voltage-error ampli- fier (vea). the combined action of the two inner current loops and the output voltage loop corrects the output voltage errors and forces the phase currents to be equal. max5037a q4 q3 c39 1 f c40 0.1 f r3 d2 q2 d1 v in c8?11 4 x 22 f q1 v in v in = +8v to +28v v cc d4 d3 c41 0.1 f c12 0.47 f c38 4.7 f c3?7 5 x 22 f load v out = +1.1v to +1.85v at 52a l2 0.6 h r2 1.35m ? l1 0.6 h r1 1.35m ? 23 dh1 24 lx1 25 dl1 22 bst1 27 v cc 28 v dd 32 dh2 31 lx2 30 dl2 34 bst2 csp2 csn2 pgood phase sgnd pgnd clp2 clp1 r11 pgood v cc r6 c35 c36 r5 c33 c34 39 40 9 41 5, 20, 35 29 43 7 c42 0.1 f c1, c2 2 x 47 f r13 2.2 ? v cc c31 c32 r4 csp1 16 csn1 17 sense+ 10 sense- 11 in 28 clkin 38 pllcmp 42 en 19 r10 r8 r7 r9 r12 c43 v in dac inputs 18 cntr 15 reg 14 eaout 13 ean 12 diff 6 ovpin 8 ovpout 4 vid0 3 vid1 2 vid2 1 vid3 44 vid4 note: see table 2 for component values. c13 0.47 f c14, c15 2 x 100 f c16?25 2 x 270 f c26?30, c37 6 x 10 f figure 2. typical vrm application circuit, v in = +8v to +28v
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 15 v in , v cc, and v dd the max5037a accepts an input voltage range of +4.75v to +5.5v or +8v to +28v. all internal control circuitry oper- ates from an internally regulated nominal voltage of 5v. for input voltages of +8v or greater, the internal v cc reg- ulator steps the voltage down to +5v. the v cc output voltage is a regulated 5v output capable of sourcing up to 80ma. bypass v cc to sgnd with 4.7f and 0.1? low- esr ceramic capacitors in parallel for high-frequency noise rejection and stable operation (figure 1). v cc powers all internal circuitry. v dd is derived exter- nally from v cc and provides power to the high-side and low-side mosfet drivers. v dd is internally connected to the power source of the low-side mosfet drivers. use v dd to charge the boost capacitors that provide power to the high-side mosfet drivers. connect the v cc regulator output to v dd through an r-c lowpass fil- ter. use a 1 ? (r3) resistor and a parallel combination of 1? and 0.1? ceramic capacitors to filter out the high peak currents of the mosfet drivers from the sensitive internal circuitry. calculate power dissipation in the max5037a as a product of the input voltage and the total v cc regulator output current (i cc ). i cc includes quiescent current (i q ) and gate drive current (i dd ): p d = v in x i cc i cc = i q + f sw x (q g1 + q g2 + q g3 + q g4 ) where, q g1 , q g2 , q g3, and q g4 are the total gate charge of the low-side and high-side external mosfets, i q is 4ma (typ), and f sw is the switching fre- quency of each individual phase. for applications utilizing a +5v input voltage, disable the v cc regulator by connecting in and v cc together. undervoltage lockout (uvlo)/soft-start the max5037a includes an undervoltage lockout with hysteresis and a power-on reset circuit for converter turn-on and monotonic rise of the output voltage. the uvlo circuit monitors the v cc regulator output while actively holding down the power-good (pgood) out- put. the uvlo threshold is internally set between +4.0v and +4.5v with a 200mv hysteresis. hysteresis at uvlo eliminates ?hattering?during startup. most of the internal circuitry, including the oscillator, turns on when the input voltage reaches +4v. the max5037a draws up to 4ma of current before the input voltage reaches the uvlo threshold. the compensation network at the current-error amplifi- er, clp1 and clp2, provides an inherent soft-start to the vrm power supply. it includes a parallel combina- tion of capacitors (c34, c36) and resistors (r5, r6) in series with other capacitors (c33, c35) (see figure 1). the voltage at clp_ limits the maximum current avail- able to charge output capacitors. the capacitor on clp_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus the output voltage. internal oscillator the internal oscillator generates the 180 out-of-phase clock signals required by the pulse-width modulation (pwm) circuits. the oscillator also generates the 2v p-p voltage ramp signals necessary for the pwm compara- tors. connect clkin to sgnd to set the internal oscillator frequency to 250khz or connect clkin to v cc to set the internal oscillator to 500khz. clkin is a cmos logic clock for the phase-locked loop (pll). when driven externally, the internal oscillator locks to the signal at clkin. a rising edge at clkin starts the on cycle of the pwm. ensure that the exter- nal clock pulse width is at least 200ns. clkout pro- vides a phase-shifted output with respect to the rising edge of the signal at clkin. phase sets the amount of phase shift at clkout. connect phase to v cc for 120 of phase shift, leave phase unconnected for 90 of phase shift, or connect phase to sgnd for 60 of phase shift with respect to clkin. the max5037a requires compensation on pllcmp even when operating from the internal oscillator. the device requires an active pll in order to generate the proper clock signal required for pwm operation. control loop the max5037a uses an average-current-mode control scheme to regulate the output voltage (figure 3). the main control loop consists of an inner current loop and an outer voltage loop. the inner loop controls the out- put currents (i phase1 and i phase2 ), while the outer loop controls the output voltage. the inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system. (1) (2)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 16 ______________________________________________________________________________________ the current loop consists of a current-sense resistor, r s (an rc lowpass filter in the case of lossless inductor current sensing), a current-sense amplifier (ca_), a current-error amplifier (cea_), an oscillator providing the carrier ramp, and a pwm comparator (cpwm_). the precision ca_ amplifies the sense voltage across r s by a factor of 18. the inverting input to the cea_ senses the output of the ca_. the output of the cea_ is the difference between the voltage-error amplifier out- put (eaout) and the amplified voltage from the ca_. the rc compensation network connected to clp1 and clp2 provides external frequency compensation for the respective cea_. the start of every clock cycle enables the high-side drivers and initiates a pwm on cycle. comparator cpwm_ compares the output volt- age from the cea_ with a 0 to 2v ramp from the oscilla- tor. the pwm on cycle terminates when the ramp volt- age exceeds the error voltage. the outer voltage control loop consists of the differen- tial amplifier (diff amp), adaptive voltage-positioning (avp) block, digital-to-analog converter (dac), and voltage-error amplifier (vea). the unity-gain differential amplifier provides true differential remote sensing of the output voltage. the differential amplifier output and the avp connect to the inverting input (ean) of the vea. the noninverting input of vea is internally connected to the dac output. the vea controls the two inner current loops (figure 3). use a resistive feedback network to set the gain of the vea as required by the adaptive voltage-positioning circuit. drive 2 drive 1 cpwm1 cpwm2 cea1 cea2 vea diff amp ca1 ca2 dac clp2 csp2 csn2 clp1 csn1 csp1 sense+ sense- v in v in load c out v out r in * r f * r s r s i phase1 i phase2 r cf c cff c cf r cf c ccf c cf avp *r f and r in are external to max5037a (r f = r8, r in = r7, figures 1 and 2). max5037a figure 3. max5037a control loop
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 17 current-sense amplifier the differential current-sense amplifier (ca_) provides a dc gain of 18. the maximum input offset voltage of the current-sense amplifier is 1mv and the common-mode voltage range is -0.3v to +3.6v. the current-sense ampli- fier senses the voltage across a current-sense resistor. peak-current comparator the peak-current comparator provides a path for fast cycle-by-cycle current limit during extreme fault condi- tions such as an output inductor malfunction (figure 4). note that the average current-limit threshold of 48mv still limits the output current during short-circuit condi- tions. so to prevent inductor saturation, select an out- put inductor with a saturation current specification greater than the average current limit. proper inductor selection ensures that only extreme conditions trip the peak-current comparator, such as a broken output inductor. the 112mv voltage threshold for triggering the peak-current limit is twice the full-scale average current-limit voltage threshold. the peak-current com- parator has a delay of only 260ns. current-error amplifier each phase of the max5037a has a dedicated transconductance current-error amplifier (cea_) with a typical g m of 550? and 320? output sink and source current capability. the cea_ outputs, clp1 and clp2, serve as the inverting input to the pwm comparator. clp1 and clp2 are externally accessible to provide frequency compensation for the inner current loops (figure 3). compensate cea_ such that the inductor current down slope, which becomes the up slope to the inverting input of the pwm comparator, is less than the slope of the internally generated voltage ramp (see the compensation section). pwm comparator and r-s flip-flop the pwm comparator (cpwm) sets the duty cycle for each cycle by comparing the current-error amplifier output to a 2v p-p ramp. at the start of each clock cycle, an r-s flip-flop resets and the high-side driver (dh_) turns on. the comparator sets the flip-flop as soon as the ramp voltage exceeds the clp_ voltage, thus termi- nating the on cycle (figure 4). differential amplifier the unity-gain differential amplifier (diff amp) facili- tates the output voltage remote sensing at the load (figure 3). it provides true differential output voltage sensing while rejecting the common-mode voltage errors due to high-current ground paths. sensing the output voltage directly at the load provides accurate load voltage sensing in high-current environments. the vea provides the difference between the differential amplifier output (diff) and the desired vid pro- grammed output voltage. the differential amplifier has a unity-gain bandwidth of 3mhz. the difference between sense+ and sense- regulates to the pro- grammed vid output voltage. connect sense+ to an external resistor-divider network at the output voltage to use the max5037a for output voltages higher than those allowed by the vid codes. 2 x f s (v/s) ramp clk csp_ csn_ gm in shdn clp_ drv_v cc bst_ dh_ lx_ dl_ pgnd a v = 18 pwm comparator peak current comparator 112mv s r q q g m = 550 s figure 4. phase circuit (phase 1/phase 2)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 18 ______________________________________________________________________________________ voltage-error amplifier the vea sets the gain of the voltage control loop. the vea determines the error between the differential amplifier output and the reference voltage generated from the dac. the vea output clamps to 0.9v relative to v cm (0.6v), thus limiting the average maximum current from individ- ual phases. the maximum average current-limit thresh- old for each phase is equal to the maximum clamp voltage of the vea divided by the gain (18) of the cur- rent-sense amplifier. this results in accurate settings for the average maximum current for each phase. set the vea gain using r f and r in for the amount of output voltage positioning required within the rated current range as discussed in the adaptive voltage positioning section (figure 3). adaptive voltage positioning powering new generation processors requires new techniques to reduce cost, size, and power dissipation. voltage positioning reduces the total number of output capacitors to meet a given transient response require- ment. setting the no-load output voltage slightly higher than the output voltage during nominally loaded condi- tions allows a larger downward voltage excursion when the output current suddenly increases. regulating at a lower output voltage under a heavy load allows a larger upward voltage excursion when the output current sud- denly decreases. a larger allowed voltage step excur- sion reduces the required number of output capacitors or allows for the use of higher esr capacitors. voltage positioning and the ability to operate with the mul- tiple reference voltages may require the output to regulate away from a center value. define the center value as the voltage where the output equals the vid reference volt- age at one half the maximum output current (figure 5). set the voltage-positioning window ( ? v out ) using the resistive feedback of the vea. see the adaptive voltage-positioning design procedure section and use the following equation to calculate the voltage-position- ing window: ? v out = i out x r in / (2 x g c x r f ) where r in and r f are the input and feedback resistors of the vea, g c is the current-loop transconductance, and r s is the current-sense resistor or, if using lossless induc- tor current sensing, the dc resistance of the inductor. the voltage at cntr (v cntr ) regulates to 1.2v (figure 6). the current set by the resistor r cntr is mirrored at the inverting input of the vea, centering the output volt- age-positioning window on the vid programmed output voltage. set the center of the output voltage with a resistor from cntr to sgnd in the following manner: where v out is a required value of output voltage at the corresponding i out . i out can be any value from no load to full load. r vr i r rg v vid cntr cntr in out in fc out = ? ? ? ? ? ? +? () 2 g r c s = 005 . load (a) v cntr no load 1/2 load full load voltage-positioning window v cntr + ? v out /2 v cntr - ? v out /2 figure 5. defining the voltage-positioning window (3) (4) (5) +1.2v 1x 1x 1x 1x v cc v cc ean dac_out reg cntr figure 6. adaptive voltage-positioning circuit
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 19 applying the voltage-positioning window at different vrm voltage settings requires that r reg = r f . the volt- age on reg internally regulates to the programmed vid output voltage. choose r reg to limit the current at reg to 50?. for example, for a vid setting of 1.85v, calculate the minimum allowed r reg as r reg = 1.85v/50? = 37k ? . to use larger values of r reg while maintaining the required gain of the vea, use larger values for r in . in the case of a vid voltage setting equal to v coremax at i out = 0 (no load), r cntr = from the above equa- tion (figure 7). for systems requiring v coremax as an absolute maximum voltage when i out = 0 (no load), calculate r reg using following the equation: dac inputs (vid0?id4) the dac programs the output voltage. the dac typi- cally receives a digital code, alternatively, the vid inputs are hardwired to sgnd or left open circuit. vid0?id4 logic can be changed while the max5037a is active, initiating a transition to a new output voltage level. change vid0?id4 together, avoiding greater than 1? skew between bits. otherwise, incorrect dac readings may cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. for any low-going vid step of 100mv or more, the ovp can trip because the ovp trip reference changes instantaneously with the vid code, but the converter output does not follow immediately. the converter out- put drops at a rate depending on the output capacitor, inductor load, and the closed-loop bandwidth of the converter. do not exceed a maximum vid step size of 75mv. the available dac codes and resulting output voltages (table 1) comply with intel? vrm 9.0 specification. internal pullup resistors connect the vid inputs to a nominal internal 3v supply. force the vid inputs below 0.8v for logic low or leave unconnected for logic high. output voltage accuracy with respect to the pro- grammed vid voltage is 0.8% over the -40? to +85? temperature range. r rr rr v vid reg in f in f coremax = +? ? ? ? ? ? ? 1 load (a) no load 1/2 load full load voltage-positioning window v coremax vid v coremax - ? v out /2 v coremax - ? v out /2 figure 7. limiting the voltage-positioning window (6) table 1. output voltage vs. dac codes vid inputs (0 = connected to sgnd, 1 = open circuit) output voltage (v) vid4 vid3 vid2 vid1 vid0 v out 11111 output off 11110 1.100 11101 1.125 11100 1.150 11011 1.175 11010 1.200 11001 1.225 11000 1.250 10111 1.275 10110 1.300 10101 1.325 10100 1.350 10011 1.375 10010 1.400 10001 1.425 10000 1.450 01111 1.475 01110 1.500 01101 1.525 01100 1.550 01011 1.575 01010 1.600 01001 1.625 01000 1.650 00111 1.675 00110 1.700 00101 1.725 00100 1.750 00011 1.775 00010 1.800 00001 1.825 00000 1.850
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 20 ______________________________________________________________________________________ phase-locked loop: operation and compensation the phase-locked loop (pll) synchronizes the internal oscillator to the external frequency source when driving clkin. connecting clkin to v cc or sgnd forces the pwm frequency to default to the internal oscillator fre- quency of 500khz or 250khz, respectively. the pll uses a conventional architecture consisting of a phase detector and a charge pump capable of providing 20? of output current. connect an external series combination capacitor (c31) and resistor (r4) and a parallel capacitor (c32) from pllcmp to sgnd to pro- vide frequency compensation for the pll (figure 1). the pole-zero pair compensation provides a zero at f z defined by 1 / [r4 x (c31 + c32)] and a pole at f p defined by 1 / (r4 x c32). use the following typical val- ues for compensating the pll: r4 = 7.5k ? , c31 = 4.7nf, c32 = 470pf. when changing the pll frequen- cy, expect a finite locking time of approximately 200?. the max5037a requires compensation on pllcmp even when operating from the internal oscillator. the device requires an active-phase-locked loop in order to generate the proper internally shifted clock available at clkout. mosfet gate drivers (dh_, dl_) the high-side (dh_) and low-side (dl_) drivers drive the gates of external n-channel mosfets (figure 1). the drivers?high-peak sink and source current capabil- ity provides ample drive for the fast rise and fall times of the switching mosfets. faster rise and fall times result in reduced cross-conduction losses. for modern cpu applications where the duty cycle is less than 50%, choose high-side mosfets (q1 and q3) with a moderate r ds(on) and very low gate charge. choose low-side mosfets (q2 and q4) with very low r ds(on) and moderate gate charge. the driver block also includes a logic circuit that pro- vides an adaptive nonoverlap time to prevent shoot- through currents during transition. the typical nonoverlap time is 60ns between the high-side and low-side mosfets. bst_ v dd powers the low- and high-side mosfet drivers. the high-side drivers derive their power through a bootstrap capacitor and v dd supplies power internally to the low-side drivers. connect a 0.47? low-esr ceramic capacitor between bst_ and lx_. bypass v dd to pgnd with 1? and 0.1? low-esr ceramic capaci- tors. reduce the pc board area formed by these capacitors, the rectifier diodes between v dd and the boost capacitor, the max5037a, and the switching mosfets. protection the max5037a includes output overvoltage protection (ovp), undervoltage protection (uvp), phase failure, and overload protection to prevent damage to the pow- ered electronic circuits. overvoltage protection (ovp) the ovp comparator compares the ovpin input to the overvoltage threshold. the overvoltage threshold is typ- ically +13% above the programmed vid output voltage. a detected overvoltage event latches the comparator output forcing the power stage into the ovp state. in the ovp state, the high-side mosfets turn off and the low-side mosfets latch on. use the ovpout high- current-output driver to turn on an external crowbar scr. when the crowbar scr turns on, a fuse must blow or the source current for the max5037a regulator must be limited to prevent further damage to the exter- nal circuitry. connect the scr close to the input source and after the fuse. use an scr large enough to handle the peak i 2 t energy due to the input and output capaci- tors discharging and the current sourced by the power source output. connect diff to ovpin for differential output sensing and overvoltage protection. add an rc delay to reduce the sensitivity of overvoltage circuit and avoid nuisance tripping of the converter (figure 8). for any low-going vid step of 75mv or more, the ovp can trip because the ovp trip reference changes instan- taneously with the vid code, but the converter output does not follow immediately. the converter output drops at a rate depending on the output capacitor, inductor load, and the closed-loop bandwidth of the converter. max5037a 1k ? r f r in 0.1 f ovpin diff ean eaout figure 8. ovp input delay
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 21 power-good generator (pgood) the pgood output is high if all of the following condi- tions are met (figure 9): 1) the output is within 90% to 108% of the pro- grammed output voltage. 2) both phases are providing current. 3) en is high. a window comparator compares the differential amplifi- er output (diff) against 1.08 times the programmed vid output voltage for overvoltage and 0.90 times the programmed vid output voltage for undervoltage moni- toring. the phase failure comparator detects a phase failure by comparing the current-error amplifier output (clp_) with a 2.0v reference. use a 10k ? pullup resistor from pgood to a voltage source less than or equal to v cc . an output voltage outside the comparator window or a phase failure con- dition forces the open-drain output low. the open-drain mosfet sinks 4ma of current while maintaining less than 0.2v at the pgood output. phase failure detector output current contributions from the two phases are within 10% of each other. proper current sharing reduces the necessity to overcompensate the external components. however, an undetected failure of one phase driver causes the other phase driver to run con- tinuously as it tries to provide the entire current require- ment to the load. eventually, the stressed operational phase driver fails. during normal operating conditions, the voltage level on clp_ is within the peak-to-peak voltage levels of the pwm ramp. if one of the phases fails, the control loop raises the clp_ voltage above its operating range. to determine a phase failure, the phase failure detection circuit (figure 9) monitors the output of the current amplifiers (clp1 and clp2) and compares them to a 2.0v reference. if the voltage levels on clp1 or clp2 are above the reference level for more than 1250 clock cycles, the phase failure circuit forces pgood low. overload conditions average current-mode control has the ability to limit the average current sourced by the converter during a fault condition. when a fault condition occurs, the vea out- put clamps to 0.9v with respect to the common-mode voltage (v cm = 0.6v) and is compared with the output of the current-sense amplifiers (ca1 and ca2) (see figure 3). the current-sense amplifier? gain of 18 limits the maximum current in the inductor or sense resistor to i limit = 50mv/r s . parallel operation for applications requiring large output current, parallel up to three max5037as (six phases) to triple the avail- able output current. the paralleled converters operating at the same switching frequency but different phases keep the capacitor ripple rms currents to a minimum. three parallel max5037a converters deliver up to 180a of output current. to set the phase shift of the on-board pll, leave phase unconnected for 90 of phase shift (two paralleled converters), or connect phase to sgnd for 60 of phase shift (three converters in parallel). designate one converter as master and the remaining converters as slaves. connect the master and slave con- trollers in a daisy-chain configuration as shown in figure 10. connect clkout from the master controller to clkin of the first slaved controller, and clkout from the first slaved controller to clkin of the second slaved controller. choose the appropriate phase shift for mini- mum ripple currents at the input and output capacitors. the master controller senses the output differential volt- age through sense+ and sense- and generates the diff voltage. disable the voltage sensing of the slaved controllers by leaving diff unconnected (floating). figure 11 shows a detailed typical parallel application circuit using two max5037as. this circuit provides four phases at an input voltage of 12v and an output voltage range of 1.1v to 1.85v at 104a. 8% of dac 10% of dac +2.0v phase failure detection clp2 clp1 dac_out diff pgood figure 9. power-good generator
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 22 ______________________________________________________________________________________ applications information each max5037a circuit drives two 180 out-of-phase channels. parallel two or three max5037a circuits to achieve four- or six-phase operation, respectively. figure 1 shows the typical application circuit for two- phase operation. the design criteria for a two-phase converter includes frequency selection, inductor value, input/output capacitance, switching mosfets, sense resistors, and the compensation network. follow the same procedure for the four- and six-phase converter design, except for the input and output capacitance. the input and output capacitance requirement varies depending on the operating duty cycle. the examples discussed in this data sheet pertain to a typical vrm application with the following specifications: v in = +12v v out = +1.1v to +1.85v i out(max) = 52a v coremax = vid programmed output voltage at no load avp ( ? v out ) = 120mv f sw = 250khz peak-to-peak inductor current ( ? i l ) = 10a table 2 shows a list of recommended external compo- nents (figure 1) and table 3 provides component sup- plier information. table 2. component list designation qty description c1, c2 2 47?, 16v x5r input-filter capacitors, tdk c5750x5r1c476m c3?11 9 22?, 16v input-filter capacitors, tdk c4532x5r1c226m c12, c13 2 0.47?, 16v capacitors, tdk c1608x5r1a474k c14, c15 2 100?, 6.3v output-filter capacitors, murata grm44-1x5r107k6.3 c16?25 10 270?, 2v output-filter capacitors, panasonic eefue0d271r c26?30, c37 6 10?, 6.3v output-filter capacitors, tdk c2012x5r0j106m c31 1 4700pf, 16v x7r capacitor, vishay-siliconix vj0603y471jxj c32, c34, c36 3 470pf, 16v capacitors, murata grm1885c1h471jab01 c33, c35, c43 3 0.01?, 50v x7r capacitors, murata grm188r71h103ka01 c38 1 4.7?, 16v x5r capacitor, murata grm40-034x5r475k6.3 c39 1 1.0?, 10v y5v capacitor, murata grm188f51a105 c40, c41, c42 3 0.1?, 16v x7r capacitors, murata grm188r71c104ka01 d1, d2 2 schottky diodes, on-semiconductor mbrs340t3 d3, d4 2 schottky diodes, on-semiconductor mbr0520lt1 l1, l2 2 0.6?, 27a inductors, panasonic etqp1h0r6bfx q1, q3 2 upper power mosfets, vishay-siliconix si7860dp q2, q4 2 lower power mosfets, vishay-siliconix si7886dp r1, r2 4 current-sense resistors, use two 2.70m ? resistors in parallel, panasonic erjm1wsf2m7u r3, r13 1 2.2 ? ?% resistor r4 1 7.5k ? ?% resistor r5, r6 2 1k ? ?% resistors r7 1 4.99k ? ?% resistor r8, r9 2 37.4k ? ?% resistors r11 1 10k ? ?% resistor r12 1 10 ? ?% resistor
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 23 clkin clkout sgnd pgnd in phase dl2 lx2 dh2 dl1 lx1 dh1 v cc v in eaout ean diff sense- sense+ csp2 csn2 csp1 csn1 v cc v in v in clkout sgnd pgnd in phase dl2 lx2 dh2 dl1 lx1 dh1 eaout ean clkin csp2 csn2 csp1 csn1 diff v cc v in v in clkout sgnd pgnd in phase dl2 lx2 dh2 dl1 lx1 dh1 eaout ean clkin csp2 csn2 csp1 csn1 diff v cc v in v in to other max5037s max5037a max5037a max5037a load figure 10. parallel configuration of multiple max5037as
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 24 ______________________________________________________________________________________ max5037a (master) q4 q3 c39 1 f c40 0.1 f r3 d2 q2 d1 v in c8?11 4 x 22 f q1 v in v in = +12v v cc d4 d3 c41 0.1 f c12 0.47 f c38 4.7 f c3?7 5 x 22 f l2 0.6 h r2 1.35m ? l1 0.6 h r1 1.35m ? 23 dh1 24 lx1 25 dl1 22 bst1 27 v cc 28 v dd 32 dh2 31 lx2 30 dl2 34 bst2 csp2 csn2 pgood phase clkout sgnd pgnd clp2 clp1 r11 pgood v cc r6 c35 c36 r5 c33 c34 39 40 9 41 36 5, 20, 35 29 43 7 c42 0.1 f c1, c2 2 x 47 f r13 2.2 ? c31 c32 r4 csp1 16 csn1 17 sense+ 10 sense- 11 in 28 clkin 38 pllcmp 42 ovpout 8 r10 r8 r7 r9 r12 c43 v in 18 cntr 15 reg 14 eaout 13 ean 12 diff 6 ovpin 19 en 4 vid0 3 vid1 2 vid2 1 vid3 44 vid4 c13 0.47 f c14, c15, c44, c45 2 x 100 f c16?25, c57?60 2 x 270 f c26?30, c37 6 x 10 f load v out = +1.1v to +1.85v at 104a v cc max5037a (slave) q8 q7 c62 1 f c63 0.1 f r16 d6 q6 d5 v in c51?54 4 x 22 f q5 v in d8 d7 c64 0.1 f c55 0.47 f c65 4.7 f 5 x 22 f c46?50 l4 0.6 h r15 1.35m ? l3 0.6 h r14 1.35m ? 23 dh1 24 lx1 25 dl1 22 bst1 27 v cc 28 v dd 32 dh2 31 lx2 30 dl2 34 bst2 csp2 csn2 pgood phase sgnd pgnd clp2 clp1 v cc r19 c67 c66 r18 c68 c69 39 40 9 41 5, 20, 35 29 43 7 c61 0.1 f r24 2.2 ? c70 c71 r17 csp1 16 csn1 17 sense+ 10 sense- 11 clkin 38 in 28 pllcmp 42 en 19 r23 r21 r20 r22 18 cntr 15 reg 14 eaout 13 ean 12 diff 6 ovpin 8 ovpout 4 vid4 3 vid3 2 vid2 1 vid1 44 vid0 c56 0.47 f vid4 vid3 vid2 vid1 vid0 dac inputs r25 r24 figure 11. four-phase parallel application circuit (v in = +12v, v out = +1.1v to +1.85v at 104a)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 25 number of phases selecting the number of phases for a voltage regulator depends mainly on the ratio of input-to-output voltage (operating duty cycle). optimum output-ripple cancella- tion depends on the right combination of operating duty cycle and the number of phases. use the following equation as a starting point to choose the number of phases: n ph k/d where k = 1, 2, or 3 and the duty cycle d = v out /v in. choose k to make n ph an integer number. for exam- ple, converting v in = +12v to v out = +1.75v yields bet- ter ripple cancellation in the six-phase converter than in the four-phase converter. ensure that the output load justifies the greater number of components for multi- phase conversion. generally, limiting the maximum out- put current to 25a per phase yields the most cost- effective solution. the maximum ripple cancellation occurs when n ph = k/d. single-phase conversion requires greater size and power dissipation for external components such as the switch- ing mosfets and the inductor. multiphase conversion eliminates the heatsink by distributing the power dissipa- tion in the external components. the multiple phases operating at given phase shifts effectively increase the switching frequency seen by the input/output capacitors, reducing the input/output capacitance requirement for the same ripple performance. the lower inductance value improves the large-signal response of the converter dur- ing a transient load at the output. consider all these issues when determining the number of phases neces- sary for the voltage regulator application. adaptive voltage-positioning design procedure the following steps outline the procedure for setting the adaptive voltage positioning: 1) choose the voltage-error amplifier input (ean) resistor r in > 5k ? . 2) determine a reasonable amount of excursion from the desired output voltage that the system can tol- erate and use as an estimate for the voltage-posi- tioning window, ? v out (see figures 5 and 7). 3) calculate r f from equations 22 and 23. use equa- tion 3 to verify that ? v out remains within tolerable limits. 4) calculate the centering resistor, r cntr , from equa- tion 5. r cntr sets the center of the adaptive voltage positioning such that at 1/2 full-load current, the output voltage is the desired vid programmed out- put voltage (figure 5). do not use values less than 24k ? for r cntr . 5) choose the regulation resistor, r reg , to have the same value as the feedback resistor, r f (r reg = r f ). r reg maintains the adaptive voltage-position- ing window at all vid output voltage settings. do not use values less than 37k ? for r reg . inductor selection the switching frequency per phase, peak-to-peak rip- ple current in each phase, and allowable ripple at the output determine the inductance value. selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficien- cy. the charge/discharge cycle of the gate and drain capacitances in the switching mosfets create switching losses. the situation worsens at higher input voltages, since switching losses are proportional to the square of input voltage. use 500khz per phase for v in = +5v, 250khz or less per phase for v in > +12v. table 3. component suppliers supplier phone fax website murata 770-436-1300 770-436-3030 www.murata.com on semiconductor 602-244-6600 602-244-3345 www.on-semi.com panasonic 714-373-7939 714-373-7183 www.panasonic.com tdk 847-803-6100 847-390-4405 www.tcs.tdk.com vishay-siliconix 1-800-551-6933 619-474-8920 www.vishay.com (7)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 26 ______________________________________________________________________________________ although lower switching frequencies per phase increase the peak-to-peak inductor ripple current ( ? i l ), the ripple cancellation in the multiphase topology reduces the rms ripple current of the input and output capacitor. use the following equation to determine the minimum inductance value: choose ? i l equal to about 40% of the output current per phase. since ? i l affects the output ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full-rated efficiency. choose inductors from the standard high-current, sur- face-mount inductor series available from various manu- facturers. particular applications may require custom-made inductors. use high-frequency core mate- rial for custom inductors. high ? i l causes large peak-to- peak flux excursion increasing the core losses at higher frequencies. the high-frequency operation coupled with high ? i l , reduces the required minimum inductance making possible even the use of planar inductors. the advantages of using planar magnetics include low-pro- file design, excellent current sharing between phases due to the tight control of parasitics, and low cost. for example, calculate the minimum inductance at v in(max) = +13.2v, v out = +1.75v, ? i l = 10a, and f sw = 250khz: the max5037a average current-mode control feature limits the maximum peak-inductor current and prevents the inductor from saturating. choose an inductor with a saturating current greater than the worst-case peak inductor current. use the following equation to determine the worst-case inductor current for each phase: where r sense is the sense resistor in each phase. switching mosfets when choosing a mosfet for voltage regulators, con- sider the total gate charge, r ds(on) , power dissipation, and package thermal impedance. the product of the gate charge and on-resistance of the mosfet is a figure of merit, with a lower number signifying better perfor- mance. choose mosfets optimized for high-frequency switching applications. the average current from the max5037a gate-drive output is proportional to the total capacitance it drives from dh1, dh2, dl1, and dl2. the power dissipated in the max5037a is proportional to the input voltage and the average drive current. see the v in , v cc, and v dd section to determine the maximum total gate charge allowed from all the driver outputs combined. the gate charge and drain capacitance (cv 2 ) loss, the cross-conduction loss in the upper mosfet due to finite rise/fall time, and the i 2 r loss due to rms current in the mosfet r ds(on) account for the total losses in the mosfet. estimate the power loss (pd mos _) in the high-side and low-side mosfets using the following equations: where q g , r ds(on) , t r , and t f are the upper switching mosfet? total gate charge, on-resistance at +25?, rise time, and fall time, respectively: where d = v out /v in , i dc = (i out - ? i l )/2 and i pk = (i out + ? i l )/2. where c oss is the mosfet drain-to-source capaci- tance. iiiii d rms lo dc pk dc pk ? =++ () ? () 22 1 3 pd q v f cvf ri mos lo g dd sw oss in sw ds on rms lo ? ? = () + ? ? ? ? ? ? + 2 3 14 2 2 . () iiiii d rms hi dc pk dc pk ? =++ () 22 3 pd q v f vi tt f ri mos hi g dd sw in out r f sw ds on rms hi ? ? = () + + () ? ? ? ? ? ? + 4 14 2 . () i r i l peak sense l _ . =+ 0 051 2 ? l k h min = ? () = 13 2 1 75 1 75 13 2 250 10 06 .. . . . l vvv vf i min inmax out out in sw l = ? () ? (8) (9) (10) (11) (12) (13) (14)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 27 for example, from the typical vrm specifications in the applications information section with v out = +1.75v, the high-side and low-side mosfet rms currents are 9.9a and 24.1a, respectively. ensure that the thermal impedance of the mosfet package keeps the junction temperature at least +25? below the absolute maxi- mum rating. use the following equation to calculate maximum junction temperature: t j = pd mos x j-a + t a input capacitors the discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. the switching frequency, peak inductor cur- rent, and the allowable peak-to-peak voltage ripple reflected back to the source dictate the capacitance requirement. increasing the number of phases increas- es the effective switching frequency and lowers the peak-to-average current ratio, yielding a lower input capacitance requirement. the input ripple comprises ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the capaci- tor). use low-esr ceramic capacitors with high ripple- current capability at the input. assume the contributions from the esr and capacitor discharge are equal to 30% and 70%, respectively. calculate the input capacitance and esr required for a specified ripple using the follow- ing equations: where i out is the total output current of the multiphase converter and n is the number of phases. for example, at v out = 1.75v, the esr and input capacitance are calculated for the input peak-to-peak ripple of 100mv or less yielding an esr and capaci- tance value of 1m ? and 200?. output capacitors the worst-case peak-to-peak and capacitor rms ripple current, the allowable peak-to-peak output ripple volt- age, and the maximum deviation of the output voltage during step loads determine the capacitance and the esr requirements for the output capacitors. in multiphase converter design, the ripple currents from the individual phases cancel each other and lower the ripple current. the degree of ripple cancellation depends on the operating duty cycle and the number of phases. choose the right equation from table 4 to cal- culate the peak-to-peak output ripple for a given duty cycle of two-, four-, and six-phase converters. the maxi- mum ripple cancellation occurs when n ph = k / d. the allowable deviation of the output voltage during the fast-transient load dictates the output capacitance and esr. the output capacitors supply the load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the converter. the resistive drop across the capacitor esr and capacitor discharge causes a voltage drop during a step load. use a combination of sp polymer and ceramic capacitors for better transient load and ripple/noise performance. c i n dd vf in out qsw = ? () 1 ? esr v i n i in esr out l = () + ? ? ? ? ? ? ? ? 2 (15) (16) (17) table 4. peak-to-peak output ripple current calculations no. of phases (n) duty cycle (d) (%) equation for ? i p-p 2< 50 2> 50 40 to 25 4 25 to 50 4> 50 6< 17 ? i vd lf o sw = ? () 12 ? i vv d lf in o sw = ? () ? () 21 ? i vd lf o sw = ? () 14 ? i vdd dl f o sw = ?? ()() 12 4 1 2 ? i vd d dl f o sw = ?? ()( ) 2134 ? i vd lf o sw = ? () 16
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 28 ______________________________________________________________________________________ keep the maximum output voltage deviation less than or equal to the adaptive voltage-positioning window ( ? v out ). assume 50% contribution each from the out- put capacitance discharge and the esr drop. use the following equations to calculate the required esr and capacitance value: where i step is the load step and t response is the response time of the controller. controller response time depends on the control-loop bandwidth. current limit the average current-mode control technique of the max5037a accurately limits the maximum output cur- rent per phase. the max5037a senses the voltage across the sense resistor and limits the peak inductor current (i l-pk ) accordingly. the on cycle terminates when the current-sense voltage reaches 45mv (min). use the following equation to calculate maximum cur- rent-sense resistor value: where pd r is the power dissipation in sense resistors. select 5% lower value of r sense to compensate for any parasitics associated with the pc board. also, select a noninductive resistor with the appropriate wattage rating. reverse current limit the max5037a limits the reverse current in the case that v bus is higher than the preset output voltage setting. calculate the maximum reverse current based on v clr , the reverse current-limit threshold, and the current- sense resistor: compensation the main control loop consists of an inner current loop and an outer voltage loop. the max5037a uses an average current-mode control scheme to regulate the output voltage (figure 3). i phase1 and i phase2 are the inner average current loops. the vea output provides the controlling voltage for these current sources. the inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single- pole system. a resistive feedback network around the vea provides the best possible response, since there are no capaci- tors to charge and discharge during large-signal excur- sions. the required amount of adaptive voltage positioning ( ? v out ) determines the vea gain. use the following equation to calculate the value for r f when using adaptive voltage positioning: where g c is the current-source transconductance and n is the number of phases. when designing the current-control loop ensure that the inductor downslope (when it becomes an upslope at the cea output) does not exceed the ramp slope. this is a necessary condition to avoid subharmonic oscillations similar to those in peak current-mode control with insuffi- cient slope compensation. use the following equation to calculate the resistor r cf : for example, the maximum r cf is 12k ? for r sense = 1.35m ? . r fl vr cf sw out sense 210 2 g r c s = 005 . r ir ng v f out in c out = ? i xv r reverse clr sense = 2 pd r r sense = ? 25 10 3 . r i n sense out = 0 045 . c it v out step response q = ? esr v i out esr step = ? (18) (19) (20) (21) (22) (23) (24)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller ______________________________________________________________________________________ 29 c cf provides a low-frequency pole while r cf provides a midband zero. place a zero at f z to obtain a phase bump at the crossover frequency. place a high-frequency pole (f p ) at least a decade away from the crossover frequency to reduce the influence of the switching noise and achieve maximum phase margin. use the following equations to calculate c cf and c cff : pc board layout use the following guidelines to lay out the switching voltage regulator. 1) place the v in , v cc, and v dd bypass capacitors close to the max5037a. 2) minimize the area and length of the high-current loops from the input capacitor, upper switching mosfet, inductor, and output capacitor back to the input capacitor negative terminal. 3) keep short the current loop formed by the lower switching mosfet, inductor, and output capacitor. 4) place the schottky diodes close to the lower mosfets and on the same side of the pc board. 5) keep the sgnd and pgnd isolated and connect them at one single point close to the negative termi- nal of the input filter capacitor. 6) run the current-sense lines cs+ and cs- very close to each other to minimize the loop area. similarly, run the remote voltage sense lines sense+ and sense- close to each other. do not cross these critical signal lines through power cir- cuitry. sense the current right at the pads of the current-sense resistors. 7) avoid long traces between the v dd bypass capaci- tors, driver output of the max5037a, mosfet gates, and pgnd. minimize the loop formed by the v dd bypass capacitors, bootstrap diode, bootstrap capacitor, max5037a, and upper mosfet gate. 8) place the bank of output capacitors close to the load. 9) distribute the power components evenly across the board for proper heat dissipation. 10) provide enough copper area at and around the switching mosfets, inductor, and sense resistors to aid in thermal dissipation. 11) use 4oz copper to keep the trace inductance and resistance to a minimum. thin copper pc boards can compromise efficiency since high currents are involved in the application. also, thicker copper conducts heat more effectively, thereby reducing thermal impedance. chip information transistor count: 5431 process: bicmos c fr cff pcf = 1 2 c fr cf zcf = 1 2 vid3 1 vid2 2 vid1 3 vid0 4 sgnd 5 ovpin 6 clp1 7 ovpout 8 pgood 9 sense+ 10 sense- 11 n.c 33 dh2 32 lx2 31 dl2 30 pgnd 29 in 28 v cc 27 v dd 26 dl1 25 lx1 24 dh1 23 vid4 44 clp2 43 pllcmp 42 phase 41 csp2 39 csn2 40 clkin 38 n.c. 37 clkout 36 sgnd 35 bst2 34 diff 12 ean 13 eaeout 14 reg 15 csp1 16 csn1 17 cntr 18 en 19 sgnd 20 n.c. 21 bst1 22 max5037a mqfp/thin qfn* *connect the qfn exposed pad to sgnd ground plane. pin configuration (25) (26)
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller 30 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) mqfp44.eps
max5037a vrm 9.0/vrm 9.1, dual-phase, parallelable, average-current-mode controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm 1 d rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k dallas semiconductor detail b e l l1 proprietary information document control no. approval title: rev. 2 2 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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